Reduced instruction buffer for RISC architectures

External memory communication is one of the most limiting factors to processor performance. In this paper, a new mechanism is presented for RISC architectures and, in general, for those architectures with a fixed pipelined structure and data references generated by load/store instructions. The mechanism is based on the restricted use of and on-chip instruction buffer (RIB) to avoid those structural hazards generated by concurrent instruction/data memory accesses. An important area saving and performance improvement can be obtained when comparing with traditional on-chip instruction cache approaches.